The First Replacement for MESI in 40 Years

Atomic Ownership Transfer: O(1) Cache Coherence for 1,000+ Core Processors

Origin 22 LLC — Provisional Patent Filed

April 2026

The Protocol That Stopped Scaling

In 1984, Papamarcos and Patel published the MESI protocol — Modified, Exclusive, Shared, Invalid — to maintain cache coherence across multi-core processors. When one core writes to a cache line, MESI broadcasts an invalidation message to every other core that might hold a copy. Those cores acknowledge. Only then does the write proceed.

For 2–4 cores, this works fine. The cost of broadcasting to 1–3 other cores is negligible.

For 128 cores, every write to a shared cache line triggers 127 invalidation messages and waits for 127 acknowledgments. The write latency scales linearly with core count. The silicon fights itself.

Every multi-core processor shipped since 1984 uses MESI or a derivative (MOESI, MESIF). No commercial alternative has been deployed in 40 years. The semiconductor industry has responded to MESI's scaling failure with workarounds — bigger caches, wider buses, snoop filters, directory-based protocols — all designed to reduce the cost of invalidation without questioning whether invalidation is the right model.

The scaling numbers tell the story:

A 128-core AMD EPYC operates at 35% efficiency on contended workloads. Sixty-five percent of the silicon is wasted on coherence overhead. Every data center on Earth is paying for transistors that spend most of their time waiting for invalidation acknowledgments.

Atomic Ownership Transfer

We replace the entire invalidation model with a single primitive: atomic ownership transfer. Ownership of a cache line transfers in one clock cycle via an atomic swap. No invalidation broadcast. No acknowledgment round-trip. No waiting.

The Critical Difference

When a core writes to a cache line under MESI, it must:

1. Send invalidation messages to all N sharers
2. Wait for N acknowledgments
3. Only then proceed with the write

Cost: O(N) messages, O(N) latency.

Under Atomic Ownership Transfer, the write completes in a single cycle. No broadcast. No acknowledgments. No waiting.

Cost: O(1). Always. Regardless of core count.

The previous owner is not notified. Stale data is detected lazily — no core ever blocks another core. No reader blocks a writer. No writer blocks a reader.

The coherence overhead shifts from eager notification (MESI) to lazy discovery — and the cost drops from O(N) to O(1).

Simulation Results

Benchmarked via RTL simulation across core counts:

At 4 cores, MESI generates 988,371 invalidation messages per million operations. Atomic Ownership Transfer generates 1,024 ownership transfers. That is a 940× reduction in coherence traffic.

MESI throughput decreases with more cores. At 64 cores, MESI delivers 0.7M ops/sec — worse than at 1 core. The protocol degrades under the exact conditions modern hardware creates. Atomic Ownership Transfer delivers 34.6M ops/sec at 64 cores — 48.5× faster.

Hierarchical Synchronization Domains

The chip organizes cores into a hierarchical structure that limits coherence scope. Most ownership transfers resolve locally within a cluster. Only cross-cluster data access escalates to a higher level. The hierarchy is self-similar — the same protocol operates at every scale.

This locality principle is why the architecture scales to 1,000+ cores: coherence traffic stays local by default, and the cost of a write is determined by data locality, not total core count.

Performance Summary

What This Means for Chips

The Core Count Wall Is Gone

MESI is why core counts plateaued. Adding more cores to a MESI chip adds more invalidation traffic, which degrades performance. The industry hit a wall at 64–128 cores not because of lithography or power — but because the coherence protocol couldn't scale beyond it.

Atomic Ownership Transfer removes this ceiling. O(1) coherence means adding cores adds linear throughput. A 1,000-core processor is architecturally feasible. The scaling limit shifts from coherence to interconnect bandwidth — a solvable physical problem, not a fundamental protocol limitation.

The Power Problem Shrinks

MESI invalidation broadcasts consume interconnect bandwidth and drive cache snooping activity across the chip. At 64 cores, the coherence fabric is the largest source of dynamic power on the die. Reducing coherence traffic by 940× directly reduces the power consumed by the interconnect, the snoop filters, and the cache controllers.

The implication for data centers: the silicon itself becomes more power-efficient. Not through smaller transistors or lower voltages — through eliminating the work the silicon was wasting on a 40-year-old protocol.

The CHIPS Act Opportunity

The U.S. CHIPS Act allocated $52 billion to restore domestic semiconductor manufacturing. The assumption was that fabrication is the bottleneck. But fabrication produces chips running MESI — the same coherence protocol on the same architecture, just manufactured domestically.

Atomic Ownership Transfer is an architectural leap, not a manufacturing one. A domestic chip designed with O(1) coherence and fabricated under the CHIPS Act would leapfrog existing architectures in performance per watt — not by shrinking transistors, but by eliminating the protocol that wastes them.

Comparison to Academic Work

The closest academic approaches:

Every prior approach optimizes around MESI's invalidation model. This work replaces it.

IP & Availability

Provisional patent filed covering the lock-free chip architecture, including the atomic ownership transfer mechanism, stale detection logic, and hierarchical domain controllers.

Available for licensing to semiconductor companies, national programs (CHIPS Act), and defense agencies. The architecture is fabrication-agnostic — implementable at any process node, any foundry.

Contact

Zachary Kent Reynolds
Origin 22 LLC
zach@origin22.com
origin22.com

Per chaos ad astra.